SEAS

Dreampal team

Dynamically Reconfigurable Architectures and Languages

Leader: Vlad Rusu

PRESENTATION MEMBERS THESES PUBLICATIONS

Presentation

Standard Integrated Circuits are reaching their limits and need to evolve in order to meet the requirements of next-generation computing. One of the most promising evolutions are the next-generation 3D FPGAs (three-dimensional Field Programmable Gate Arrays), which will allow efficient dynamic reconfigurations in a massively parallel manner. Software applications running on such architectures can efficiently reconfigure the underlying hardware at runtime according to their needs, thereby achieving significant savings in circuit space, energy consumption and execution time. This new hardware paradigm opens many opportunities for research since there are no execution models or dedicated tools for safely programming software applications on them. We thus address the following topics: designing massively parallel dynamically reconfigurable architectures; proposing execution models as well as dedicated programming languages for them; and designing software-engineering tools for those languages: compilers, emulators, and formal verifiers, for enabling the rigorous, efficient, and safe programming of software applications on the new hardware. Our target application domain is safety-critical embedded applications performing intensive computation.

Members

Permanent

  • Professor
    • Jean-Luc Dekeyser
  • Associate professors
    • Frédéric Guyomarc’H
    • Philippe Marquet
    • Samy Meftali
  • Research scientist
    • Vlad Rusu (Responsable)

Temporary

  • Phd student
    • Wissem Chouchene
  • Engineer
    • Awais Sani

Wissem Chouchene

Advanced 3D FPGA Technology for Dynamic Reconfigurable Massively Parallel Architectures

Hana Krichene

SCAC: modèle d'exécution faiblement couplé pour les systèmes massivement parallèles sur puce 2015-10-23

Andrei Arusoaie

A generic framework for symbolic execution with applications to program verification 2014-09-27

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