on the web page of team “Émeraude” of the CRIStAL and IRCICA labs.

Scientific project

The project of the Émeraude team is to contribute to the efficient and easy usage of future generation processors for mobile and embedded applications with a focus on time in all the layers of computation (language, compiler, operating system, virtual machine).

According to the ITRS and HiPEAC roadmaps, the processor makers face several challenging problems:

  • The limit on the power dissipation of the chips (130 W for desktop computers, 25 W for laptop computers and 5 W for tablets and smartphones) that severly limits the operating frequency of the processors and has given rise to the multicores.
  • The end of Dennard’s scaling the causes the “dark silicon” effect, that leads to specialization of the multiple cores on a chip.
  • The physical limits of CMOS scaling that cause more and more variability in the manufacturing processes and will put an end to Moore’s law in the next decade.

At the same time, the application world is rapidly changing with the booming of mobile computing on smartphones and tablets, and the coming of age of the internet of things. Such mobile and embedded devices applications often have mixed criticality parts with some tasks that must respect deadlines while others are best effort. Without the need to rely too much on legacy software, this is a wonderfull occasion to rethink computation to make it more efficient in this new context.

Main direction: use time to better adapt

The core idea we will develop in our research is that by using timing information, the operating system or middleware will be empowered to make better decisions concerning the power consumption. For example, knowing a deadline and having an estimation of the needed processing power for a task could allow to reduce the operating frequency, and thus reduce energy consumption.

Our research will contribute to energy aware real-time scheduling on heterogeneous platforms, task and communication mapping on heterogeneous networks-on-chips, and runtime dynamic adaptation to the hardware variability. We will validate our propositions mainly by simulation, but also by prototyping. Indeed, we will apply our results in the domain of augmented reality on mobile devices because such applications exhibit mixed criticality tasks (e.g. video processing vs text rendering) with energy limits (battery capacity). We have started a pluri-disciplinary collaboration with other labs (IEMN, LgCGE) on the “smart campus” project of Univ. Lille 1.

The main international reference on this subject is the Ptolemy project of Pr Edward A. Lee. We are involved in Europe in the HiPEAC network of excellence and are part of the EMSIG community. In France, we find our place in the community of the Architecture axis of the ASR GdR (chaired by Pierre Boulet) that includes actions about the scientific domains related to our research: embedded systems, real-time, compilation, architecture, …

Risk taking: neuro-inspired accelerators

In addition to this core research direction, we study the possibility to radically change the way we compute by using neuro-inspired accelerators based on emerging memristive devices. We have started to explore potential architectures of hardware neural networks based on memristors. Indeed, these emergent nanoelectronic devices have a behavior that is remarquably similar to the behavior of synapses in a biological neural network. To this effect, we collaborate with two teams of the IEMN nanotechnology labs to build a simulator using the characteristics of the devices they design and to research proposals of architectures of hardware neural networks based on these devices.

This emerging technology has a great potential to overcome the variability issue of CMOS scaling, and to strongly reduce the power consumption of future computation devices, but presents lots of challenges in terms of manufacturability, architecture, and integration in a digital computation. Our research focus in particular on the integration between traditional digital processors and such hardware neural network accelerators.

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