List of Publications

 

2013


2012Top

Peer reviewed International Journals

  1. Chtioui H., Niar S., Ben Atitallah R., Zahran  M., Dekeyser J-L., Aabid M. A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC  architectures. International Journal of Computer Applications (IJCA), 11,
  2. M Elhaji, A Zitouni, S Meftali, JL Dekeyser, R Tourki A Low-Power Oriented Architecture for H. 264 variable block size motion estimation based on a resource sharing scheme, Integration, the VLSI Journal, 2012. 
  3.  Abdallah A., Gamatie A., Ben Atitallah R., Dekeyser J-L. . Abstract Clock-based Design of a JPEG Encoder. IEEE Embedded Systems Letters, volume: pp, issue: 99.
  4.  Antonio Wendell De Oliveira Rodrigues, Frédéric Guyomarc'H; Jean-Luc Dekeyser; Yvonnick Le Menach Automatic Multi-GPU Code Generation Applied to Simulation of Electrical Machines Magnetics, IEEE Transactions on, IEEE Magnetics Society, 2012, 48 (2), pp. 831 - 834
  5. Imran Rafiq Quadri, Abdoulaye Gamatie, Pierre Boulet, Samy Meftali and Jean-Luc Dekeyser Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: advantages, limitations and alternatives, Journal of Systems Architecture: Embedded Software Design (JSA). January 2012.

Book chapters

  1. A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile.Gilberto Ochoa-Ruiz; Ouassila Labbani; El-Bay Bourennane; Philippe Soulard; Sana Cherif Design Automation for Embedded Systems, Springer Verlag (Germany), 2012

Peer reviewed Conferences and Workshop

  1. Viswanathan V., Ben Atitallah R., Dekeyser J-L., Nakache B., Nakache M.. Dynamic Reconfiguration of Modular I/O IP cores for Avionic Applications, International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012). Cancun, Mexique, décembre.
  2. Pamela Wattebled  ; Jean-Philippe Diguet  ; Jean-Luc Dekeyser Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems RecoSoc 2012, Jul 2012, YORK, United Kingdom
  3. Rethinagiri S-K., Ben Atitallah R., Senn E., Dekeyser J-L., Niar S. (2012). An Efficient Power Estimation Methodology for Complex RISC Processor based Embedded Platforms. 22nd Great Lakes Symposium on VLSI (GLSVLSI 2012), Salt Lake City, Utah, USA, mai.
  4. Afonso G., Ben Atitallah R., Dekeyser J-L.  Software Implementation vs. Hardware Implementation: The Avionic Test System Case-Study. Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012), London, United Kingdom, mars.
  5.  Gilberto Ochoa-Ruiz, Sana Cherif, Ouassila Labbani-Narsis, El-Bay Bourennane, Samy Meftali and Jean-Luc Dekeyser Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study, International Conference on Reconfigurable Computing and FPGAs (Reconfig 2012), Cancun, Mexico, December 5-7, 2012.
  6.  Gilberto Ochoa-Ruiz, Sana Cherif, Ouassila Labbani, El-Bay Bourennane, Samy Meftali and Jean-Luc Dekeyser Enabling partially reconfigurable IP cores parameterization and integration using IP-XACT and MARTE, IEEE International Symposium on Rapid System Prototyping, Tampere, Finland, October 2012.
  7.  Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser Semi-distributed control for FPGA-based reconfigurable systems, September 2012. DSD Conference. Turquey.
  8.   Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser Distributed control for reconfigurable FPGA systems: a high-level design approach, Workshop Recosoc. 2012.

2011Top

Peer reviewed International Journals

  1. Ben Atitallah R., Piel E., Niar S., Marquet  P., Dekeyser J-L. A Fast MPSoC Virtual Prototyping for Intensive Signal Processing Applications. Microprocessors and Microsystems Embedded Hardware Design Journal (MICPRO), 36 issue 3, pp. 176–189
  2. Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser and Abderrazek Jemai A model-driven approach for hybrid power estimation in embedded systems design, EURASIP Journal on Embedded Systems (2011)
  3. Aydi Yassine, Baklouti Mouna, Dekeyser Jean-Luc, Abid Mohamed. A Multi-Level Design Methodology of Multistage Interconnection Network for MPSOCs. International Journal of Computer Applications in Technology (IJCAT), Inderscience Publishers, 2011, 42 (1-2)
  4. A. Abdallah, A. Gamatié, J.-L. Dekeyser. Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone, in: RSTI - TSI - 30/2011. Architecture des ordinateurs, 2011, vol. 30, p. 1089 – 1114.

Book chapters

  1. Dekeyser Jean-Luc, Gamatié Abdoulaye, Meftali Samy, Quadri Imran Rafiq. Models for Co-Design of Heterogeneous Dynamically Reconfigurable SoCs. Ian O Connor. Heterogeneous Embedded Systems - Design Theory and Practice, Springer, 26 p., Jan. 2011
  2. Aydi Yassine, Baklouti Mouna, Marquet Philippe, Dekeyser Jean-Luc, Abid Mohamed. A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture. Mohamed Khalgui and Hans-Michael Hanisch. Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, IGI-Global, pp. 209-234, 2011

Peer reviewed Conferences and Workshop

  1. Rethinagiri S-K., Ben Atitallah, R., Senn E., Niar S., Dekeyser J-L. Fast and Accurate Hybrid Power Estimation Methodology for Embedded Systems. Conference on Design &  Architectures for Signal & Image  Processing, Tampere FL, novembre. (2011)
  2. Rethinagiri S-K., Ben Atitallah, R., Dekeyser J-L.  A System Level Power Consumption Estimation for MPSoC. International Symposium on System-on-Chip 2011 (SOC 2011), Tampere, Finland, octobre.
  3. Rethinagiri S-K., Ben Atitallah, R., Niar S., Senn E., Dekeyser J-L.  Hybrid System Level Power Consumption Estimation for FPGA-Based MPSoC. International Conference on Computer Design (ICCD'11), Best paper awards, septembre.
  4. S. Cherif, C. Trabelsi, S. Meftali, J.-L. Dekeyser.High Level Design of adaptive distributed controller for Partial Dynamic reconfiguration in FPGA, in: Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, September 2011.
  5. M. Elhaji, B. Attia, A. Zitouni, R. Tourki, S. Meftali, J.-L. Dekeyser.FERONOC : Flexible and extensible router implementation for diagonal mesh topology, in: Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, September 2011.
  6. G. Afonso, R. Ben Atitallah, J.-L. Dekeyser.A Design Environment for Reconfigurable Computing Systems, in: Systems-on-Chip - System-in-Package, Lyon, France, June 2011.
  7. Afonso G., Ben Atitallah, R., Loyer A., Dekeyser J-L., Belanger N., Rubio M.  A prototyping environment for high performance reconfigurable computing. 6th International Workshop on Reconfigurable and Communication-centric Systems-on-Chip, Montpellier, France, juin.
  8. Afonso G., Ben Atitallah R., Belanger N., Rubio M., Stilkerich S., Dekeyser J-L. Toward Generic and Adaptive Avionic Test Systems. NASA/ESA Conference on Adaptive Hardware and Systems, San Diego, California, USA, juin.
  9. Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology, DASIP 2011. Tempere. Finlande.
  10. Antonio Wendell de Oliveira Rodrigues, Frederic Guyomarch and Jean-Luc Dekeyser Programming Massively Parallel Architectures using MARTE: a case study, M-BED 2011 Grenoble Mars 2011
  11. Majdi Elhaji, Adbelkrim Zitouni and Rached Tourki, Pierre Boulet, Samy Meftali and Jean-Luc Dekeyser, Modelling Networks-on-Chip at System Level with the MARTE UML profile, M-BED 2011 Grenoble Mars 2011

Reports / Poster Presentations

  1. De Oliveira Rodrigues Antonio Wendell, Guyomarc'H Frédéric, Dekeyser Jean-Luc. An MDE Approach for Automatic Code Generation from MARTE to OpenCL. [Research Report], 2011, pp. 27. RR-7525

2010Top

Peer reviewed International Journals

  1. M. Baklouti, Y. Aydi, Ph. Marquet, J.L. Dekeyser and M. Abid , Scalable mpNoC for massively parallel systems – Design and implementation on FPGA Journal of Systems Architecture 2010
  2. Yu Huafeng, Gamatié Abdoulaye, Rutten Éric, Dekeyser Jean-Luc. Adaptivity in High-Performance Embedded Systems: a Reactive Control Model for Reliable and Flexible Design. Knowledge Engineering Review, Cambridge university press, 2010, 21 p.
  3. Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Anne Etien, Rabie Ben Atitallah, Philippe Marquet, Jean-Luc Dekeyser. A Model Driven Design Framework for Massively Parallel Embedded Systems. ACM Transactions in Embedded Computing Systems (TECS), 2010.
  4. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. A Model based design flow for Dynamic Reconfigurable FPGAs. International Journal of Reconfigurable Computing, 2010.
  5. Quadri Imran Rafiq, Yu Huafeng, Gamatié Abdoulaye, Meftali Samy, Dekeyser Jean-Luc, Rutten Éric. Targeting Reconfigurable FPGA based SoCs using the MARTE UML profile: from high abstraction levels to code generation. International Journal of Embedded Systems, InderScience Publishers, 2010, 18 p
  6. Aydi Yassine, Abid Mohamed, Dekeyser Jean-Luc. Design and Performance Estimation of Delta Networks for MPSOC on Programmable Circuits. International Journal on Sciences and Techniques of Automatic control & computer engineering (IJ-STA), Academic Publication Center, 2010, 4 (1), pp. 1126-1137

Book chapters

  1. Imran Rafiq Quadri, Majdi Elhaji, Samy Meftali, Jean-Luc Dekeyser. Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication. Chap. 0, IGI-Global, 2010.
  2. Le Beux Sébastien, Moss Laurent, Marquet Philippe, Dekeyser Jean-Luc. A High Level Synthesis Flow Using Model Driven Engineering. Gogniat, G.; Milojevic, D.; Morawiec, A.; Erdogan, A. Algorithm-Architecture Matching for Signal and Image Processing, 73, Springer, pp. 253-274, Nov. 2010, Lecture Notes in Electrical Engineering, 978-90-481-9964-8

Peer reviewed Conferences and Workshop

  1. Quadri Imran Rafiq, Meftali Samy, Dekeyser Jean-Luc. Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. Conference on Design and Architectures for Signal and Image Processing (DASIP 2010), 26/10/2010-28/10/2010, Edinburgh, United Kingdom.
  2. Aranega Vincent, Mottu Jean-Marie, Etien Anne, Dekeyser Jean-Luc. Using Traceability to Enhance Mutation Analysis Dedicated to Model Transformation. Workshop on Model driven Engineering Verification and Validation, 03/10/2010, Olso, Norway.
  3. Aranega Vincent, Etien Anne, Dekeyser Jean-Luc. Using an Alternative Trace for QVT. Workshop on Multi-Paradigm Modeling, 03/10/2010, Olso, Norway.
  4. Cherif Sana, Quadri Imran Rafiq, Meftali Samy, Dekeyser Jean-Luc. Modeling reconfigurable Systems-on-Chips with UML MARTE profile: an exploratory analysis. 13th Euromicro Conference on Digital System Design (DSD 2010), 01/09/2010-03/09/2010, Lille, France.
  5. Baklouti Mouna, Marquet Philippe, Dekeyser Jean-Luc, Abid Mohamed. IP based configurable SIMD massively parallel SoC. 20th International Conference on Field Programmable Logic and Applications, FPL 2010, 31/08/2010-02/09/2010, Milano, Italy.
  6. Quadri Imran Rafiq, Gamatié Abdoulaye, Boulet Pierre, Dekeyser Jean-Luc. Modeling of Configurations for Embedded System Implementations in MARTE. 1st workshop on Model Based Engineering for Embedded Systems Design - Design, Automation and Test in Europe (DATE 2010), 08/03/2010-12/03/2010, Dresden, Germany.
  7. Trabelsi Chiraz, Meftali Samy, Ben Atitallah Rabie, Jemai Abderrazak, Luc Dekeyser Jean, Niar Smail. An MDE Approach for Energy Consumption Estimation in MPSoC Design. 2nd Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 24/05/2010, Pisa, Italy. 6 p.
  8. Abdallah Adolf, Gamatié Abdoulaye, Dekeyser Jean-Luc. Correct and Energy-Efficient Design of SoCs: the H.264 Encoder Case Study. International Symposium on System-on-Chip (SoC'2010), Best paper award, 28/09/2010-30/09/2010, Tampere, Finland.
  9. Baklouti Mouna, Marquet Philippe, Dekeyser Jean-Luc, Abid Mohamed. Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. 6th International Symposium on Applied Reconfigurale Computing, ARC 2010, 17/03/2010-19/03/2010, Bangkok, Thailand. Springer, Reconfigurable computing: Architectures, tools and applications, 5992, pp. 110-121, Lecture Notes in Computer Science.
  10. Elhaji M., Boulet Pierre, Meftali S., Zitouni A., Dekeyser J., Tourki R.. An MDE approach for modeling network on chip topologies. Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, 03/2010, Hammamet, Tunisia.
  11. Afonso G., Ben atitallah R., Belanger N., Rubio M., Dekeyser J-L.  An Efficient Design Methodology for Hybrid Avionic Test Systems. 15th IEEE International Conference on Emerging Techonologies and Factory Automation, Bilbao, Spain, janvier.

2009Top

Peer reviewed International Journals

  1. Abdoulaye Gamatié, Éric Rutten, Huafeng Yu, Pierre Boulet and Jean-Luc Dekeyser. Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems. Scalable Computing: Practice and Experience (SCPE), 10(2), 2009.

Peer reviewed Conferences and Workshop

  1. Wendell De Oliveira Rodrigues, Frédéric Guyomarch, Jean-Luc Dekeyser, Yvonick Le Menach. Parallel Sparse Matrix Solver on the GPU Applied to Simulation of Electrical Machines. In Compumag, Florianapolis, Brazil, November 2009.
  2. Imran Rafiq Quadri, Yassin Elhillali, Samy Meftali, Jean-Luc Dekeyser. Model based design flow for implementing an Anti-Collision Radar system. In 9th International IEEE Conference on ITS Telecommunications (ITS-T 2009), Lille, France, October 2009.
  3. Imran Rafiq Quadri, Alexis Muller, Samy Meftali, Jean-Luc Dekeyser. MARTE based design flow for Partially Reconfigurable Systems-on-Chips. In 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 09), Florianapolis, Brazil, October 2009.
  4. Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser. Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. In SYMPosium en Architecture de machines (SympA'13), Toulouse, France, September 2009.
  5. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs. In International Conference on Design and Architectures for Signal and Image Processing (DASIP 09), Nice, France, September 2009.
  6. Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser. Model-Driven Design of Embedded Multimedia Applications on SoCs. In 12th Euromicro Conference on Digital System Design (DSD2009), Patras, Greece, August 2009.
  7. Hajer Chtioui, Rabie Ben Atitallah, Smail Niar, Mohamed Abid, Jean-Luc Dekeyser. A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoCs. In 12th Euromicro Conference on Digital System Design (DSD2009), Patras, Greece, August 2009.
  8. Vincent Aranega, Jean-Marie Mottu, Anne Etien, Jean-Luc Dekeyser. Traceability Mechanism for Error Localization in Model Transformations. In 4th International Conference on Software and Data Technologies (ICSOFT 2009), To Appear, Sofia, Bulgaria, July 2009.
  9. Mouna Baklouti, Philippe Marquet, Muhammad Abid, Jean-Luc Dekeyser. Study and Integration of a Parametric Neighbouring Interconnection Network in a Massively Parallel Architecture on FPGA. In The 7th ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-2009), Rabat, Morocco, May 2009.
  10. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. MARTE based design approach for targeting Reconfigurable Architectures. In 2nd International Conference on Embedded Systems (ESC'09), Invited Paper, Alger, Algeria, May 2009.
  11. Jean-Luc Dekeyser, Imran Rafiq Quadri, Abdoulaye Gamatié. Tutorial: Using the UML profile for MARTE to MPSoC co-design dedicated to signal processing. In Colloque International Télécom 2009 et 6èmes Journées JFMMA, Invited Paper, Agadir, Morocco, March 2009.

Reports and  Presentations

  1. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. From MARTE to dynamically reconfigurable FPGAs : Introduction of a control extension in a model based design flow. Research Report INRIA, No 6862, March 2009

2005-08Top

Peer reviewed International Journals

  1. Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet and Jean-Luc Dekeyser. Synchronous Modeling and Analysis of Data Intensive Applications. EURASIP Journal on Embedded Systems, 2008.
  2. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser. Safe Design of High-Performance Embedded Systems in an MDE framework. Innovations in Systems and Software Engineering (ISSE), 4(3), 2008.
  3. Éric Piel, Philippe Marquet, Jean-Luc Dekeyser. Model Transformations for the Compilation of Multi-processor Systems-on-Chip. Generative and Transformational Techniques in Software Engineering II, 5235/2008:459-473, October 2008.
  4. Luc Charest, Philippe Marquet, Jean-Luc Dekeyser, El Mostapha Mostapha Aboulhamid, Guy Bois. Using design pattern for type unification, structural unification, semantic clarification and introspection in SystemC. Annals for Micro and Nano Systems, 2007.
  5. Samy Meftali, Joël Vennin, Jean-Luc Dekeyser. An Optimized Distributed Simulation Environment for SoC Design. Annals for Micro and Nano Systems, 2007.
  6. Ahmad Chadi Chadi Aljundi, Jean-Luc Dekeyser, Mohan Tahar Tahar Kechadi and Isaac D. Scherson. A Universal Performance Factor for Multi-Criteria Evaluation of Multistage Interconnection Networks. Future Generation Computer Systems, 22(7):794-804, 2006.
  7. Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser. Safe Design Methodology for an Intelligent Cruise Control System with GPS. IEEE Intelligent Transportation Systems Society Newsletter, 8(4):16-23, December 2006.
  8. S. Meftali, J. Vennin, J.-L. Dekeyser An optimized distributed simulation environment for SoC design, Annals for Micro and Nano Systems, 2006.

Book chapters

  1. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser. Embedded Systems Specification and Design Languages, Selected papers from FDL 2007. Chap. 0, pp. 183-198, Lecture Notes in Electrical Engineering, Springer, 2008.
  2. Lossan Bondé, Cédric Dumoulin, Jean-Luc Dekeyser. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'04. Chap. 0, CHDL, Springer, 2007.
  3. Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. Advances in Design and Specification Languages for SoCs, Selected contributions from FDL'06. Chap. 0, CHDL, Springer, 2007.
  4. Abdelkader Amar, Pierre Boulet, Jean-Luc Dekeyser. Algorithms and Tools for Parallel Computing On Heterogeneous Clusters. ISBN: 1-60021-049-X, ISBN: 1-60021-049-X, Chap. 0, Nova Science Publishers, Inc, 2006.
  5. Lossan Bondé, Cédric Dumoulin, Jean-Luc Dekeyser. Advances in Design and Specification Languages for SoCs. Chap. 6, Kluwer Academic, 2005.
  6. Arnaud Cuccuru, Philippe Marquet, Jean-Luc Dekeyser.  UML 2 as an ADL, IFIP International Federation for Information Processing. Vol. 176, Chap.pp. 133-147, Springer, January 2005.
  7. L. Bondé , P. Boulet , A. Cuccuru , J.-L. Dekeyser , C. Dumoulin , P. Marquet .Model Driven Engineering for Distributed Real-time Embedded Systems, S. Gérard, J.-P. Babau, J. Champeau (editors), ISTE, 2005, chap.: Model-Driven Architecture for Intensive Embedded Systems.

Peer reviewed Conferences and Workshop

  1. Neji B., Aydi Y., Ben Atitallah R., Meftali S., Abid M., Dekeyser J-L. (2008). Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA. The 3rd International Design and Test Workshop, Monastir, Tunisia, décembre.
  2. Mouna Baklouti, Philippe Marquet, Muhammad Abid, Jean-Luc Dekeyser. A Design and an implementation of a parallel based SIMD architecture for SoC on FPGA. In Conference on Design and Architectures for Signal and Image Processing (DASIP 2008), Bruxelles, Belgium, November 2008.
  3. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. A Design Space Exploration Flow for FPGA implementation of Intensive Signal Processing Applications. In Special Session on Formal Models, Transformations and Architectures for Reliable Embedded System Design, in Conference on Design and Architectures for Signal and Image Processing (DASIP 2008), Bruxelles, Belgium, November 2008.
  4. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. In 6th IEEE Workshop on Embedded Systems for Real-Time Multimedia, Atlanta, USA, October 2008.
  5. Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser. MARTE-based Design of a Multimedia Application and Formal Analysis. In Forum on specification and design languages (FDL'08), Stuttgart, Germany, September 2008.
  6. Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet and Jean-Luc Dekeyser. Modeling and Formal Validation of High-Performance Embedded Systems. In 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), Krakow, Poland, July 2008.
  7. Jehangir Khan, Smail Niar, Yassin Elhilali, Jean-Luc Dekeyser. An MPSoC Architecture for the Multiple Target Tracking Application in Driver Assistant System. In 19th IEEE International Conference Application-specific Systems, Architectures and Processors (ASAP'08), Leuven, Belgium, July 2008.
  8. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. High Level Modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE. In Reconfigurable Communication-centric SoCs (ReCoSoC'08), Barcelona, Spain, July 2008.
  9. Asma Charfi, Abdoulaye Gamatié, Antoine Honoré, Jean-Luc Dekeyser, Mohamed Abid. Validation de modèles dans un cadre d'IDM dédié à la conception de systèmes sur puce. In 4èmes Jounées sur l'Ingénierie Dirigée par les Modèles (IDM 08), Pages 1-18, Mulhouse, France, June 2008.
  10. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. A MDE design flow for implementing Partially Dynamically Reconfigurable FPGAs. In 2nd Colloque Nationale of GDR SOC-SIP, Paris, France, June 2008.
  11. Julien Taillard, Frédéric Guyomarch, Jean-Luc Dekeyser. OpenMP code generation based on an Model Driven Engineering approach. In The 2008 High Performance Computing & Simulation Conference (HPCS 2008), Nicosia, Cyprus, June 2008.
  12. Jean-Luc Dekeyser, Abdoulaye Gamatié, Anne Etien, Rabie Ben Atitallah, Pierre Boulet. Using the UML Profile for MARTE to MPSoC Co-Design. In First International Conference on Embedded Systems & Critical Applications (ICESCA'08), Tunis, Tunisia, May 2008.
  13. Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser. Using An MDE Approach for Modeling of Interconnection networks. In The International Symposium on Parallel Architectures, Algorithms and Networks Conference (ISPAN 08), Sydney, Australia, May 2008.
  14. Éric Piel, Rabie Ben Atitallah, Philippe Marquet, Samy Meftali, Smaïl Niar, Anne Etien, Jean-Luc Dekeyser, Pierre Boulet. Gaspard2: from MARTE to SystemC Simulation. In Proceeedings of the DATE'08 workshop on Modeling and Analyzis of Real-Time and Embedded Systems with the MARTE UML profile, March 2008.
  15. Hajer Chtioui, Rabie Ben Atitallah, Smail Niar, Mohamed Abid, Jean-Luc Dekeyser. Gestion de la cohérence des caches dans les architectures MPSoC utilisant des NoC complexes. In Rencontres francophones du Parallélisme (RenPar'18) / Symposium en Architecture de machines (SympA '2008 ) / Conférence Française sur les Systèmes d'Exploitation (CFSE '6), Fribourg, Switzerland, February 2008.
  16. Julien Taillard, Frédéric Guyomarch, Jean-Luc Dekeyser. A Graphical Framework for High Performance Computing using an MDE Approach. In 16th Euromicro International Conference on Parallel, Distributed and network-based Processing, Pages 165-173, Toulouse, France, February 2008.
  17. Jean-Luc Dekeyser, Sébastien Le Beux, Rabïe Ben Atitallah and Éric Piel. Transformations multiples d'un modèle d'application pour la simulation sur MPSoC et la synthèse sur FPGA. In Ecole d'hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes, Montebello, Canada, January 2008.
  18. Sébastien Revol, Safouan Taha, François Terrier, Alain Clouard, Sébastien Gérard, Ansgar Radermacher, Jean-Luc Dekeyser. Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT. In DIPES'2008 IFIP conference, volume 271, Springer Verlag, Pages 69-78,, 2008.
  19. Yassine Aydi, Samy Meftali, Mohamed Abid, Jean-Luc Dekeyser. Design and Performance Evaluation of a Reconfigurable Delta MIN for MPSOC. In 19th International Conference on Microelectronics (ICM'07), Cairo, Egypt, December 2007.
  20. Rabie Ben Atitallah, Smail Niar, Jean-Luc Dekeyser. MPSoC Power Estimation Framework at Transaction Level Modeling. In The 19th International Conference on Microelectronics (ICM 2007), Cairo, Egypt, December 2007.
  21. Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. An MDE Approach for Implementing Partial Dynamic Reconfiguration in FPGAs. In 16th International Conference on IP Based System-on-chip, IP'07, Grenoble, France, December 2007.
  22. Yassine Aydi, Samy Meftali, Mohamed Abid, Jean-Luc Dekeyser. Dynamicity Analysis of Delta MINs for MPSOC Architectures. In Conference internationale des sciences et = technique de l'automatique (ICM'07), Sousse, Tunisie, November 2007.
  23. Jean-Luc Dekeyser, Sébastien Le Beux, Philippe Marquet. Une approche modèle pour la conception conjointe de systèmes embarqués hautes performances dédiés au transport. In Workshop International : Logistique & Transport (LT' 2007), (In French), Sousse, Tunisie, November 2007.
  24. Rabie Ben Atitallah, Éric Piel, Smail Niar, Philippe Marquet, Jean-Luc Dekeyser. Multilevel MPSoC simulation using an MDE approach. In IEEE International SoC Conference (SoCC 2007), Hsinchu, Taiwan, September 2007.
  25. Rabie Ben Atitallah, Éric Piel, Julien Taillard, Smail Niar, Jean-Luc Dekeyser. From High Level MPSoC description to SystemC Code Generation. In International ModEasy'07 Workshop in conjunction with Forum on specification and Design Languages (FDL'07), Barcelona, Spain, September 2007.
  26. Sébastien Le Beux, Philippe Marquet, Antoine Honoré, Jean-Luc Dekeyser. A Model Driven Engineering Design Flow to Generate VHDL. In International ModEasy'07 Workshop, Barcelona, Spain, September 2007.
  27. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser. Model Transformations from a Data Parallel Formalism towards Synchronous Languages. In Forum on specification and design languages (FDL'07), Pages 183-198, Barcelona, Spain, September 2007.
  28. Rabie Ben Atitallah, Smail Niar, Samy Meftali, Jean-Luc Dekeyser. An MPSoC Performance Estimation Framework Using Transaction Level Modeling. In The 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Daegu, Korea, August 2007.
  29. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. A Design Flow to Map Parallel Applications onto FPGAs. In 17th IEEE International Conference on Field Programmable Logic and Applications, Amsterdam, Netherlands, August 2007.
  30. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. Multiple Abstraction Views of FPGA to Map Parallel Applications. In Reconfigurable Communication-centric SoCs 2007 (ReCoSoC'07), Montpellier, France, June 2007.
  31. Safouan Taha, Ansgar Radermacher, Sebastien Gerard, Jean-Luc Dekeyser. An Open Framework for Detailed Hardware Modeling. In IEEE Second International Symposium on Industrial Embedded Systems, Lisbon, Portugal, June 2007.
  32. Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser. Massively Parallel Processing on a Chip. In ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.
  33. Jean-Luc Dekeyser, Lossan Bondé. Une Approche modèle dans la conception de systèmes sur puce hétérogènes. In Ecole d'hiver Francophone sur les Technologies de Conception des systèmes embarqués Hétérogènes, Villard-de-Lans, France, January 2007.
  34. Simon Duquennoy, Sébastien Le Beux, Philippe Marquet, Samy Meftali, Jean-Luc Dekeyser. MpNoC Design: Modeling and Simulation. In 15th IP Based SoC Design Conference (IP-SoC 2006), Grenoble, France, December 2006.
  35. Rabie Ben Atitallah, Lossan Bonde, Smail Niar, Samy Meftali and Jean-Luc Dekeyser. Multilevel MPSoC Performance Evaluation Using MDE Approach. In International Symposium on System-on-Chip 2006 (SOC 2006), Invited paper, Tampere, Finland, November 2006.
  36. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet and Jean-Luc Dekeyser. Synchronous Modeling of Data-Intensive Applications. In International Open Workshop on Synchronous Programming (Synchron 2006), Alpe d'Huez, France, November 2006.
  37. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Pierre Boulet and Jean-Luc Dekeyser. Vers des transformations d'applications à parallélisme de données en équations synchrones. In 9e édition de SYMPosium en Architectures nouvelles de machines (SympA'2006), Pages 166-177, Perpignan, France, October 2006.
  38. Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. UML2 Profile for Modeling Controlled Data Parallel Applications. In Forum on specification and Design Languages (FDL'06), Darmstadt, Germany, September 2006.
  39. Ouassila Labbani, Éric Rutten, Jean-Luc Dekeyser. Safe Design Methodology for an Intelligent Cruise Control System with GPS. In 64th IEEE Vehicular Technology Conference (VTC 2006), Montréal, Québec, Canada, September 2006.
  40. Sébastien Le Beux, Vincent Gagné, El Mostapha Mostapha Aboulhamid and Philippe Marquet, Jean-Luc Dekeyser. Hardware/Software Exploration for an Anti-collision Radar System. In 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico, August 2006.
  41. Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser. FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. In 9th Euromicro Conference on Digital System Design (DSD'2006), Dubrovnik, Croatia, August 2006.
  42. Rabie Ben Atitallah, Smail Niar, Samy Meftali, Jean-Luc Dekeyser. Accelerating MPSoC Performance Evaluation with TLM. In "Advanced Computer Architecture and compilation for Embedded Systems ACACES", HIPEAC network of Excellence summer school, ISBN 90 382 0981 9, Pages 229-232, Laquilia, Italy, July 2006.
  43. Eric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser. Real-Time Systems for Multi-Processor Architectures. In 14th International Workshop on Parallel and Distributed Real-Time Systems, In conjunction with IPDPS, 20th IEEE International Parallel and Distributed Processing Symposium, Invited paper, Island of Rhodes, Greece, April 2006.
  44. Rabie Ben Atitallah, Smail Niar, Alain Greiner, Samy Meftali and Jean-Luc Dekeyser. Estimating Energy Consumption for an MPSoC Architectural Exploration. In Architecture of Computing Systems (ARCS'06), Frankfurt, Germany, March 2006.
  45. Julien Taillard, Jean-Luc Dekeyser, Francis Piriou. A Design of a UML Profile for Meta-computing. In 14th Euromicro Conference on Parallel, Distributed and Network-based Processing (PDP 2006), Montbéliard-Sochaux, France, February 2006.
  46. Ali Koudri, Samy Meftali, Jean-Luc Dekeyser. IP integration in embedded systems modeling. In 14th IP Based SoC Design Conference (IP-SoC 2005), Grenoble, France, December 2005.
  47. Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson. Scalable Multistage Networks for Multiprocessor System-on-Chip Design. In 8th International Symposium on Parallel Architectures, Algorithms, and Networks, Las Vegas, Nevada, USA, December 2005.
  48. Julien Taillard, Philippe Marquet, Jean-Luc Dekeyser. Embedded Linux Co-simulation. In IP Based SoC Design Conference (IP-SoC 2005), Grenoble, France, December 2005.
  49. Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet. Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies - A partial answer to the MARTE RFP. In MoDELS/UML 2005, ACM/IEEE 8th International Conference on Model Driven Engineering Languages and Systems, Pages 445-459, Montego Bay, Jamaica, October 2005.
  50. O. Labbani , J.-L. Dekeyser , P. Boulet , E. Rutten .Introducing Control in the Gaspard2 Data-Parrallel MetaModel: Synchronous Approach, in: MARTES '05, International Workshop on Modelling and Analysis of Real-Time and Embedded Systems, (in conjunction with 8th International Conference on Model Driven Engineering Languages and Systems, MoDELS/UML 2005), Montego bay, Jamaica, October 2005,
  51. Lossan Bondé, Pierre Boulet, Jean-Luc Dekeyser. Traceability and Interoperability at Different Levels of Abstraction in Model Transformations. In Forum on Specification and Design Languages, FDL'05, Lausanne, Switzerland, September 2005.
  52. Samy Meftali, Anouar Dziri, Luc Charest, Philippe Marquet and Jean-Luc Dekeyser. SOAP Based Distributed Simulation Environment for System-on-Chip (SoC) Design. In Forum on Specification and Design Languages, FDL'05, Lausanne, Switzerland, September 2005
  53. Eric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser. Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. In Workshop on Scheduling for Parallel Computing (SPC 2005), ©Springer-Verlag, Poznan, Poland, September 2005.
  54. Joël Vennin, Stéphane Penain, Luc Charest, Samy Meftali and Jean-Luc Dekeyser. Embedded Scripting inside SystemC. In Forum on Specification and Design Languages (FDL'05), Lausanne, Switzerland, September 2005
  55. Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena. Model Driven Engineering for Regular MPSoC Co-design. In ReCoSoC-05, Montpellier, France, June 2005.
  56. Jean-Luc Dekeyser, Pierre Boulet, Philippe Marquet, Samy Meftali. Model Driven Engineering for SoC Co-Design. Invited speaker In NEWCAS'05, Québec, Québec, June 2005.
  57. Laurent Rioux, Thierry Saunier, Sébastien Gérard, Ansgar Radermacher, Robert de Simone, Thierry Gautier, Yves Sorel and Julien Forget, Jean-Luc Dekeyser, Arnaud Cuccuru, Cédric Dumoulin, Charles André. MARTE: A New OMG Profile RFP for the Modeling and Analysis of Real-Time Embedded Systems. In DAC 2005 Workshop UML for SoC Design (UML-SoC'05), Anaheim, CA, USA, June 2005.
  58. Jean-Luc Dekeyser, Philippe Marquet, Samy Meftali, Cédric Dumoulin, Pierre Boulet, Smail Niar. Why to do Without Model Driven Architecture in Embedded System Codesign?. In The first annual IEEE BENELUX/DSP Valley Signal Processing Symposium, (SPS-DARTS 2005), Antwerp, Belgium, April 2005.
  59. Philippe Marquet, Éric Piel, Julien Soula, Jean-Luc Dekeyser. ARTiS, un système d'exploitation temps-réel asymétrique. In 4e édition de la Conférence Française sur les Systèmes d'Exploitation (CFSE'4), (In French), Le Croisic, France, April 2005.
  60. Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet. Mode-Automata based Methodology for Scade. In Hybrid Systems: Computation and Control, 8th International Workshop, Springer (ed.), LNCS series, Pages 386-401, Zurich, Switzerland, March 2005.

Reports / Poster Presentations

  1. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. Model Driven Engineering Benefits for High Level Synthesis. Research Report INRIA, No 6615, 2008.
  2. Abdoulaye Gamatié, Sébastien Le Beux, Éric Piel, Anne Etien, Rabie Ben Atitallah, Philippe Marquet, Jean-Luc Dekeyser. A Model Driven Design Framework for High Performance Embedded Systems. Research Report INRIA, No 6614, August 2008.
  3. Rabie Ben Atitallah, Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Antoine Honoré, Ouassila Labbani, Sébastien Le Beux, Philippe Marquet, Éric Piel, Julien Taillard, Huafeng Yu. Gaspard2 UML profile documentation. Technical Report INRIA, No 342, September 2007.
  4. Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Jean-Luc Dekeyser. Model Transformations from a Data Parallel Formalism towards Synchronous Languages. Research Report INRIA, No 6291, September 2007.
  5. Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser. Modeling of topologies of Interconnection Networks based on Multidimensional Multiplicity. Research Report INRIA, No 6201, May 2007.
  6. Abdoulaye Gamatié, Eric Rutten, Huafeng Yu, Pierre Boulet and Jean-Luc Dekeyser. Synchronous Modeling of Data Intensive Applications. Research Report INRIA, No 5876, April 2006.
  7. Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. Separating Control and Data Flow: Methodology and Automotive System Case Study. Research Report INRIA, No 0, January 2006.
  8. Ouassila Labbani, Jean-Luc Dekeyser, Pierre Boulet, Éric Rutten. Introducing Control in the Gaspard2 Data-Parallel Metamodel: Synchronous Approach. Research Report INRIA, No 0, January 2006.
  9. Sébastien Le Beux, Vincent Gagné, El Mostapha Mostapha Aboulhamid and Philippe Marquet, Jean-Luc Dekeyser. Hardware/Software Exploration for an Anti-collision Radar System. Research Report INRIA, No 5820, January 2006.
  10. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser. FPGA Configuration of Intensive Multimedia Processing Tasks Modeled in UML. Research Report INRIA, No 0, January 2006.
  11. Éric Piel, Philippe Marquet, Julien Soula, Christophe Osuna, Jean-Luc Dekeyser. ARTiS, an Asymmetric Real-Time Scheduler for Linux on Multi-Processor Architectures. Research Report INRIA, No 0, December 2005.

Before 2005Top

Publications internationales (revues avec comité de lecture)

  1. J-L Dekeyser "Synchronisation by indirect action mechanism in Ada" Journal of Pascal, Ada and Modula2 Vol 5 Num 6 pp 5-23 Nov 86
  2. J.-L. Dekeyser, C. Georgiopoulos "Vectorization of the Geant3 geometrical routines on a Cyber 205" Nuclear Instruments and Methods in Physics Research A264: 291-296,1988
  3. U. Chandra, J.-L. Dekeyser, F. Hannedouche, G. Riccardi, et J. Vagi .<AFTRAN ; an array FORTRAN programming language,>Computer Physics Communications 57:263--267, 1989.
  4. Jean-Luc Dekeyser et Christian Lefebvre, "HPF-Builder: A visual environment to transform Fortran90 codes to HPF", International Journal of Supercomputer Applications and High Performance Computing (Special Issue)-- Volume 11.2 (Summer 1997)
  5. T Kechadi et J-L Dekeyser, "Analysis and Simulation of an Out-of-Order Execution Model in Vector Multiprocessor Systems", Parallel Computing, North Holland , Dec 1997, V23N13, pp 1963-1986
  6. C Fonlupt, P Marquet et J-L Dekeyser, "Data Parallel Load Balancing Strategies", Parallel Computing, North Holland ,1998, V24, pp 1665-1684

Ouvrages ou chapitres d'ouvrage

  1. J-L Dekeyser et P Marquet,"Supporting Irregular and Dynamic Computations in Data Parallel Languages", Spring School on Data Parallelism. Mars 96 LNCS tutorials series PP197-219, Springer Verlag

Publications internationales (revues avec comité de sélection)

  1. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<EVA: an explicit vector language --- An alternate to FORTRAN 90,>ACM Sigplan Notices 25(8):53--71, aug 1990.
  2. J.-L. Dekeyser, D. Lazure, et Ph. Marquet.<A geometrical data-parallel language> ACM Sigplan Notices 29(4):31--40, april 1994.

Revues nationales

  1. Jean-Luc Dekeyser, Cyril Fonlupt et Philippe Marquet,"Équilibrage de Charge sur Machine SIMD", La Lettre des Calculateurs Parallèles et Distribués", Vol 6, 1994, pp45-48
  2. Fabien Banse, Jean-Luc Dekeyser, Renaud Fauquembergue,"Parallélisation d'une méthode de Monte Carlo pour la simulation de composants semi-conducteurs",TSI Vol 19, N°8, 2000.

Publication de communications internationales (colloques avec actes publiés et comité de programme)

  1. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<Vector addressing processor for direct and indirect accesses,>Euromicro' 90, Amsterdam, The Netherlands, 27--30 aug, 1990. In Microprocessing and Microprogramming 29(1):657--664, aug 1990.
  2. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<A multi-level environment for data-parallel code generation> Proc. Esprit European Workshops on Parallel Computing (EWPC'92), Barcelone, Espagne, 23--24 mar, 1992. IOS Press 252-255
  3. J.-L. Dekeyser, D. Lazure et Ph. Marquet,<HELP for Parallel Scientific Programming> Euromicro Workshop On Parallel and Distributed Processing, p 22-29. Gran Canaria, January 27-29, 1993. IEEE Computer Society Press.
  4. Akram Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet<HelpDraw graphical environment: A step beyond data parallel programming languages>. In Michael J. Smith Gavriel Salvendy, editor,Human-Computer Interaction: Software and Hardware Interfaces.Proceedings of the Fifth
  5. International Conference on Human-Computer Interaction, (HCI'93). Volume 2, pages 591-596, Orlando, Florida, August 8-13 1993. Elsevier Science Publishers B.V.
  6. J.-L. Dekeyser, C. Fonlupt et Ph. Marquet,"A data parallel view of the load balancing" HPCN Europe 94, Munich, avril 94. Lecture notes in computer sciences, Springer Verlag 797 pp338-343 00070193.
  7. Cyril Fonlupt and Philippe Marquet and Jean-Luc Dekeyser,"Analysis of Synchronous Dynamic Load Balancing Algorithms", ParCo'95, Gent, Belgium, Sep 95, Parallel Computing: State of the Art and perspectives 1996, North Holland, pp455-462
  8. Dominique Sueur, Jean-Luc Dekeyser"Dynamic Redistribution on Heterogeneous Parallel computers",Europar 96, Lyon, Aout 1996, Europar'96 Parallel Processing, Springer Verlag, LNCS 1123, pp173-178
  9. Galinec, J.-L. Dekeyser, P. Marquet,"A mixed synchronous-asynchronous approach for digital signal procesing", Proceedings of the Third International Conference on Signal Processing, Beijing, China, Vol. I, pp. 158-161, IEEE press, 1996.
  10. Jean-Luc Dekeyser, Boris Kokoszko, Jean-Luc Levaire et Philippe Marquet,"Irregular data parallel objects in C++" VECPAR'96 -- Second International Meeting on Vector and Parallel Processing (Systems and Applications), Porto, 25-27 September 1996. LNCS1215, pp65-80
  11. Pierre Boulet, Jean-Luc Dekeyser, Florent Devin, and Philippe Marquet."A visual development environment for meta-computing applications." In HCI International 2001, 9thInt'l Conf. on Human-Computer Interaction, New Orleans, LA, August 2001. Lawrence Erlbaum Associates, Publishers.
  12. Julien Soula and Philippe Marquet and Jean-Luc Dekeyser and Alain Demeure,"Compilation Principle of a Specification Language Dedicated to Signal Processing",, Sixth International Conference on Parallel Computing Technologies, PaCT 2001, Novosibirsk, Russia, LNCS.

Communications internationales (colloques avec actes et comité de programme)

  1. D Levinthal, H Goldman, C Georgiopoulos, J-L Dekeyser, S Linn, S Youssef et M Houdous, "Supercomputing at FSU", FSU-SCRI-87-11, Conference on computing in high energy physics, Asilomar State Beach CA, Fev 87
  2. J.-L. Dekeyser et Ph. Preux.<Indirect memory decoding for vector access> Int'l Symp. on Computer Architecture and Digital Signal Processing, Hong-Kong, oct 1989, pages 293--298.
  3. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<EVA: an explicit vector language> 10 SCCC Int'l Conf. on Computer Science, Santiago, Chili, 23--27 jul, 1990, pages 233--244.
  4. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<PARTNER: an environment for parallel scientific computing> Proc. ISMM Workshop on Parallel Computing, Trani, Italie, 10--13 sep, 1991, pages 288--291.
  5. J.-L. Dekeyser, M. T. Kechadi, Ph. Marquet, et Ph. Preux.<Disordered vector pipelined processor> Proc. ISMM Workshop on Parallel Computing, Trani, Italie, 10--13 sep, 1991, pages 36--39.
  6. A. Benalia, J.-L. Dekeyser, D. Lazure, P. Marquet"HelpDraw: an interactive graphical environment for data parallel programming." CNI/MAT'92 International Workshop, P. I-03, Nancy ,Dec 9-11, 1992.
  7. J.-L. Dekeyser, M. T. Kechadi, Ph. Marquet,"An Out-of-Order Execution Model for Vector Pipeline Multiprocessor Systems", Workshop on Parallel and Distributed Processing -- WP&DP'93,Sofia, Bulgarie, Mai 1993.
  8. D. Lazure, J-L Dekeyser, Ph. Marquet."HELP: A Model to Think, Write, and Run Data-Parallel Algorithms" Workshop on Parallel and Distributed Processing. Sofia, Bulgarie. Mai 1993
  9. J-L Dekeyser, D Galinec, Ph Marquet"VMMS: a virtual memory management system on MasPar" IEEE Workshop on High Performance Computing Sao Paulo, Mars 94.
  10. J.-L. Dekeyser, C. Fonlupt et Ph. Marquet,"Dynamic load-balancing on SIMD data-parallel supercomputers, Experimental results on a MasPar MP-1" EUROSIM'94, Deflt,NL, juin 94.
  11. David Galinec, Fabien Battini, Jean-Luc Dekeyser, Philippe Marquet"An asynchronous run-time model for a synchronous approach of real-time problems" Proceedings of the International Conference on Telecommunication, Distribution and Parallelism, La Londe les Maures, France, June 26-28, 1996
  12. David Galinec, Jean-Luc Dekeyser, Philippe Marquet"Distributing Signal and Real-Time Image Processing Applications" CADR'96 Computer-Aided Design International Conference in Russia, September 1-6, 1996, Gelengick, RUSSIA
  13. David Galinec, Jean-Luc Dekeyser, Philippe Marquet"Mixed Synchronous-Asynchronous Approach for Real-Time Image Processing: A MPEG-like Coder" Proceedings of the IEEE International Conference on Image Processing, ICIP'96, Lausanne, Switzerland, 1996, Vol. II, pp. 121-124
  14. Dominique Sueur, Jean-Luc Dekeyser"DpShell: A Data parallel File System" SIAM Conference on Parallel Processing for Scientific Computing, Mineapolis 14-17 Mars 1997
  15. F Banse, J-L Dekeyser, R Fauquembergue, F Dessenne,"Implementation of a Bi-Parallel Monte Carlo Device Simulation on Two Architectures",HPCN 98, Amsterdam, 21 Avril 1998
  16. Christian Lefebvre and Jean-Luc Dekeyser,"Visualization of HPF data mappings and of their communication cost", VecPar'98, Porto Juin 1998
  17. E. Cagniot, T. Brandes, J.L. Dekeyser, F. Piriou, P. Boulet andS.Clenet,"High Level Parallelization of a 3D Electromagnetic Simulation Code With Irregular Communication Patterns", 4th International Meeting on Vector and Parallel Processing (VECPAR'2000), Porto, Portugal, June 2000"High Level Parallelization of a 3D Electromagnetic Simulation Code With Irregular Communication Patterns", 4th International Meeting on Vector and Parallel Processing (VECPAR'2000), Porto, Portugal, June 2000
  18. E. Cagniot, T. Brandes, J.L. Dekeyser, F. Piriou, P. Boulet and G. Marques,"Parallelization of 3D Magnetostatic Code Using High Performance Fortran",International Conference on Parallel Computing in Electrical Engineering (PARELEC'2000)Trois-Rivières, Québec, Canada, August 27-30, 2000:
  19. Pierre Boulet, Jean-Luc Dekeyser, Jean-Luc Levaire, Philippe Marquet, Julien Soula, and Alain Demeure."Visual data-parallel programming for signal processing applications." 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, Mantova, Italy, February 2001.
  20. E. CAGNIOT, T. BRANDES, J.L. DEKEYSER, F. PIRIOU :Parallelization of a 3D Magnetostatic Code Using High Performance Fortran and the Schur Complement Method, 13th Conference on the Computation of Electromagnetic Fields (COMPUMAG'13), Evian, France, 2001
  21. Abdelkader Amar, Pierre Boulet and Jean-Luc Dekeyser,"Assembling Dynamic Components for Metacomputing using CORBA", PARCO 2001, Naples, Sept 2001.
  22. Ahmad Chadi ALJUNDI, Jean-Luc DEKEYSER, M-Tahar KECHADI,Isaac D. SCHERSON,"Comparative Simulations and Performance Evaluation of MCRB Networks Using Multidimensional Queue Management", SPECTS02, Juillet 2002, San Diego, USA
  23. F Devin, P. Boulet, J-L Dekeyser and P Marquet"GASPARD a visual parallel programming environment", Parelec 2002, Warsaw, Poland, 22 - 25 September 2002
  24. Ahmad Chadi ALJUNDI, Jean-Luc DEKEYSER, M-Tahar KECHADI,Isaac D. SCHERSON,"A study of an evaluation methodology for unbuffered multistage interconnection networks", IPDPS Workshop PMEO-PDS'03, 22 -26 April, 2003, Nice Acropolis Convention Center, Nice, France
  25. Ahmad Chadi ALJUNDI, Jean-Luc DEKEYSER and Isaac D. SHERSON,"An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks", Proceedings of the ISCA 16th International Conference on Parallel and Distributed Computing Systems, pp. 1-8, 13-15 Aug. 2003, Reno, Nevada, USA
  26. A Amar, P. Boulet, JL. Dekeyser, Frans Theeuwen:"Distributed Process Networks Using Half FIFO Queues in CORBA" Parco, Dresde, Allemagne 2-5 Sep 2003
  27. Cédric Dumoulin,Jean-Luc Dekeyser, Boris Kokoszko, Stéphane Pulon, Gérard Cristau“Interoperability between Design and Simulation tools using Model Transformation techniques ", FDL'03, Frankfurt, sept 2003
  28. Pierre Boulet Jean-Luc Dekeyser Cédric Dumoulin Philippe Marquet"MDA for SoC Simulation", FDL'03, Frankfurt, sept 2003
  29. Pierre Boulet, Jean-Luc Dekeyser, Cedric Dumoulin, Philippe Marquet,"MDA for SoC Embedded Systems Design, Intensive Signal Processing Experiment", SIVOES-MDA workshop at UML 2003, 20-24 October 2003 San Francisco
  30. Samy Meftali, Joel Vennin, Jean-Luc Dekeyser,“A fast SystemC simulation Methodology fo Multi-Level IP/SoC Design», IFIP International Workshop On IP Based System-on-Chip Design, November 2003, Grenoble
  31. Pierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Kajfasz, Philippe Marquet, and Dominique Ragot.«: Cyber-enterprise for system-on-chip distributed simulation - model unification”. IFIP International Workshop On IP Based System-on-Chip Design, November 2003, Grenoble
  32. Samy Meftali, Joel Vennin, Jean-Luc Dekeyser,“Automatic Generation of, Geographically Distributed, SystemC Simulation Models for IP/SoC Design”, 46th IEEE International MWSCAS, Cairo, Egypt, December 2003.
  33. ALJUNDI, A. CH. and DEKEYSER, J.-L.,"The Effecte of the Degree of Multistage Interconnection Networks on their Performance: the Case of Delta and Over-sized Delta Networks". 2004 Euromicro on Parallel and Distributed Processing, Coruna, Spain, 11-13 Feb. 2004.
  34. Pierre Boulet, Arnaud Cucurru, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet, Michael Samyn, Robert de Simone, Gunther Siegel, and Thierry Saunier. "MDA for SoC Design: UML To SystemC Experiment". In USOC 2004 - International Workshop on UML for SoC Design (Sponsored by DAC 2004), Jun 2004.
  35. Samy Meftali, Jean-Luc Dekeyser"An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design" The 4th IEEE International Workshop System-on-Chip for Real-Time Applications July 19 - July 21, 2004Banff, Alberta - Canada
  36. Samy Meftali, Jean-Luc Dekeyser,SoC P2P: A Peer-to-Peer IP Based SoCs Design and Simulation Tool.PRO-VE'04 : 5th IFIP Working Conference on VIRTUAL ENTERPRISES. August, 2004. Toulouse- France.
  37. Arnaud Cuccuru, Pierre Boulet, and Jean-Luc Dekeyser.Regular hardware architecture modeling with UML2. In FDL04, Lille, France, September 2004.
  38. Lossan Bondé, Cédric Dumoulin, and Jean-Luc Dekeyser.Metamodels and MDA transformations for embedded systems. In FDL04, Lille, France, September 2004.
  39. Mickaël Samyn, Samy Meftali, and Jean-Luc Dekeyser.MDA based, systemc code generation, applied to intensive signal processing applications. In FDL04, Lille, France, September 2004.
  40. Emilian Turbatu, Samy Meftali, Smaïl Niar, and Jean-Luc Dekeyser.An automatic communication synthesis for high level SoC design using transaction level modeling. In FDL04, Lille, France, September 2004.
  41. ITEA Hyades Project.Linux for high performance and real-time computing on SMP systems. In Sixth Realtime Linux Workshop, Singapore, November 2004.
  42. Philippe Marquet, Éric Piel, Julien Soula, and Jean-Luc Dekeyser.Implementation of ARTiS, an asymmetric real-time extension of SMP Linux. In Sixth Realtime Linux Workshop, Singapore, November 2004.
  43. Joël Vennin, Samy Meftali, and Jean-Luc Dekeyser.Understanding and extending SystemC user thread package to IA-64 platform. In International Workshop on IP Based SoC design, Grenoble, France, December 2004.
  44. Mickael Samyn, Samy Meftali, and Jean-Luc Dekeyser.Performances Estimation Metamodel for MDA Based SoC Design. In International Workshop on IP Based SoC design, Grenoble, France, December 2004.
  45. S. Niar , S. Meftali , J. L. Dekeyser .Power aware cache memory design with SystemC, in: 18th IEEE International Conference on MicroElectronics, Tunis, Tunisia, December 2004, http://www.gmslab.org/conferences/icm2004/.

Présentations internationales (avec sélection et actes)

  1. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<Vector programming in EVA> Supercomputing '90 (poster session), New-York, NY, 12--16 nov, 1990.
  2. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<LSD2: An embedded language for massively parallel and vector pipeline programming> Parallel Computing '91 (poster session), Londres, 3--6 sep, 1991.
  3. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<A step by step approach to transform FORTRAN code in a vector form using the embedded language LSD2> Supercomputing '91 (poster session), Albuquerque, NM, 18--22 nov, 1991.
  4. J.-L. Dekeyser, M. T. Kechadi, Ph. Marquet, et Ph. Preux.<Performance improvement for vector pipeline multiprocessor systems using a disordered execution model> Int'l Symp. on Computer Architecture (ISCA'92) (poster session),Queensland, Australie, 19--21 may, 1992.
  5. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<Load-store dependences and data-parallel code generation> CONPAR 92 -- VAPP V (Poster session), Lyon, sep 1992. Lecture Notes in Computer Sciences.
  6. A Benalia, J-L. Dekeyser, D. Lazure, Ph. Marquet."HELP for data-parallel scientific programming" Supercomputing'92. (Poster session).Minneapolis, Minnesota. Nov 16-20, 1992.
  7. Jean-Luc Dekeyser and Cyril Fonlupt and Philippe Marquet,"Data-parallel Load Balacing", Supercomputing'94 (poster session), Washington D. C.", nov 94
  8. Akram Benalia and Jean-Luc Dekeyser and Philippe Marquet,"A Graphical environment for HPF code developement", Supercomputing'94 (poster session) Washington D. C.", Nov 94
  9. Jean-Luc Dekeyser, Philippe Marquet et Boris Kokoszko,"Irregular structures in data-parallel languages", Supercomputing'95(poster session), San Diego CA, Dec 95
  10. Christian Lefebvre Jean-Luc Dekeyser"HPF-Builder: AVisual HPF directive editor" SIAM Conference on Parallel Processing for Scientific Computing(Poster Session), Mineapolis, 14-17 Mars 1997
  11. Jean-Luc Dekeyser, Philippe Marquet, "Video killed the radio star", Supercomputing'99(poster session), Portland Or, Dec 99 http://www.lifl.fr/west/gaspard
  12. E. Cagniot, J-L. Dekeyser, P. Boulet, T. Brandes, F. Piriou, G. Marques,"Parallélisation d'un code 3D magnétostatique avec le langage de programmation high performance fortran", 3ième conférence européenne sur les méthodes numériques en electromagnétisme, Poitiers, 20-22 Mars 2000

Communications internationales (sur invitation)

  1. J.-L. Dekeyser, C. Georgiopoulos"Technical report on the vectorization of Geant3" The ISSC workshop Argonne proceeding, Argonne, USA, Aout 87
  2. J-L Dekeyser"Geant3 on a Cray X/MP48: first results of the vector version on Cray" Int'l workshop on calorimeter simulation, Julich, Germany, Oct 88
  3. J.-L. Dekeyser, Ph. Marquet, et Ph. Preux.<DEVIL: an intermediate vector language, definition and implementation> Workshop on Compilers for Parallel Computers, Paris, 3--5 dec, 1990, pages 273--284.
  4. J.-L. Dekeyser.<HELP for scientific programming> 2nd Workshop on parallel Computing, Invited speaker, Sep 92, Mons Belgique.
  5. Cyril Fonlupt, Jean-Luc Dekeyser et Philippe Marquet,"Data parallel load balancing on MasPar MP1" Franco-british N+N meeting on data-parallel languages and compilers for portable parallel computing ", Lille France Avril 94.
  6. Jean-Luc Dekeyser et Philippe Marquet,"Data-parallel object classification", Franco-british N+N meeting on data-parallel languages and compilers for portable parallel computing , Lille France Avril 94
  7. F. Banse, R. Fauquembergue, J-L Dekeyser,"Implementation of a Monte Carlo 2D device simulation on a massively parallel system- Application oi a GaAs MESFET" 9th III-V Semiconductor Device Simulation Workshop, Eindhoven, 9-10 mai 1996
  8. Jean-Luc Dekeyser et Christian Lefebvre,"HPF-Builder: A visual environment to transform Fortran90 codes to HPF",Workshop on Environments and Tools For Parallel Scientific Computing , Ed J Dongarra & B Tourancheau, Faverges de la Tour, France, August 21-23, 1996
  9. Jean-Luc Dekeyser et Philippe Marquet,"Irregular data parallel languages" VECPAR'96 -- Second International Meeting on Vector and Parallel Processing (Systems and Applications), Porto, 25-27 September 1996.

Communications nationales (colloques avec actes et comité de programme)

  1. J.-L. Dekeyser, M. T. Kechadi, Ph. Marquet, et Ph. Preux<Résolution de conflits d'accès à la mémoire par désordonnancement,> RenPar4, 4es Rencontres du Parallélisme, Villeneuve d'Ascq, 18--20 mar 1992, pages 96--99.
  2. J.-L. Dekeyser, D. Lazure et Ph. Marquet,"HELP: un support géométrique pour la programmation data-parallèle" 5emes rencontres sur le parallélisme, p25-28. Brest, 26-28 Mai, 1993.
  3. J.-L. Dekeyser, C. Fonlupt et Ph. Marquet,"Distributions dynamiques de données pour machines massivement parallèles" 5emes rencontres sur le parallélisme, p183-186. Brest, 26-28 Mai, 1993.
  4. Jean-Luc Dekeyser, Cyril Fonlupt et Philippe Marquet"Equilibrage de charge pour machines parallèles synchrones: Modele, formalisme et analyse" Journées de recherches sur le placement dynamique et la repartition de charge: application aux systemes repartis et paralleles, Université P et M Curie Paris, mai 95
  5. Pierre Boulet, Jean-Luc Dekeyser, Alain Demeure, Florent Devin and Philippe Marquet,"Une approche à la SQL du traitement de données intensif dans Gaspard", RenPar'11, Rencontres Francophones du Parallélisme des Architectures et des Systèmes", pp151-156, Rennes, juin 99.
  6. E. Cagniot, T. Brandes, J.L. Dekeyser, F. Piriou," Parallélisation d'un Code Electromagnétique 3D Irrégulier Avec High Performance Fortran", Renpar'12Rencontres Francophones du Parallélisme des Architectures et des Systèmes , Besançon, France, Juin 2000
  7. E. CAGNIOT, T. BRANDES, J.L. DEKEYSER, F. PIRIOU :une Approche Génie Logiciel des Codes de Simulation Irréguliers : Application au cas de l'Electromagnétisme, 13ièmes Rencontres Francophones du Parallélisme des Architectures et des Systèmes (RENPAR'13), Paris, France

Communications, Conférences, Cours ou Publications sur invitation

  1. J.-L. Dekeyser.<Data management on a vector machine> SCRI School in vector computing in experimental high energy physics, Thallassee, USA, Juin 88
  2. J.-L. Dekeyser.<Partner : A multi-level environment for data-parallel code generation,> DPRI Symposium (Data Parallel Research Initiative TMC/DEC), Boston, apr 1992.
  3. L. Bougé, J.-L. Dekeyser, Ph. Marquet et S. Petiton,"Le parallélisme de données", Tutorial 5emes rencontres sur le parallélisme, Brest, 26-28 Mai, 1993.
  4. J.-L. Dekeyser,"Le parallélisme de données comme modèle de programmation pour le calcul scientifique" CNRS Expériences et méthodes en calcul parallèle: présent et futur, 25 Avril 94
  5. J-L Dekeyser," Classification des objets data parallel", séminaire de Loria,Nancy, 5 mai 94
  6. J-L Dekeyser,"Modèles de programmation et langages parallèles", Ecole CNRS concepts et pratique du calcul parallèle, CRIHAN, Rouen 23-27 Janv 95 et Juin 95.
  7. J-L Dekeyser" Systeme de fichiers paralleles pour machines heterogenes", Journees ParAppli, Grenoble, 6 Juin 96.
  8. Christian Lefebvre Jean-Luc Dekeyser"HPF-Builder: AVisual HPF directive programming environment" HPF User group meeting, Santa Fe, 24-27 Fevrier 1997
  9. P. Boulet J-L Dekeyser C Lefebvre D Ruckebush,"Communication pre-visualization"HPF Second User Group Meeting, Porto, Portugal, Juin 98
  10. J-L Dekeyser, P. Boulet, E. Cagniot, F. Piriou, S. Clenet, Y. Lemenach, G. Marques, T. Brandes"Paralleliszation of a Fortran 90 Program for Electromagnetic Problems", Hug'99, the 3rd Annual HPF User Group Meeting, Redondo Beach, California, August 1-2 1999
  11. J-L Dekeyser, C Dumoulin, "MDA for SoC simulation", Date'03, Fringe Workshop Sopocles, 4-6 Mars 2003, Munich
  12. J-L Dekeyser,“From UML to SystemC: Intensive signal processing application”, séminaire CETICSystemC, May 2003 Charleroi, Belgique.
  13. J-L Dekeyser,“LIFL: Co-modeling for co-design”, ECSI Letter, 2003
  14. J-L Dekeyser.,“Model Driven Architecture for Intensive Embedded Systems” summer school MDE for Embedded System, Brest - France, from September the 6th to 10th 2004